1. Field of the Invention
The present invention relates to a bus converter capable of reducing simultaneous switching noise, a semiconductor device on which the bus converter is mounted, and a method of reducing simultaneous switching noise.
2. Description of the Related Art
When data transmission is switched from a synchronous bus to an asynchronous bus, all bus signals are shifted at the timing of a synchronization signal. At that time, simultaneous switching noise is caused. Here, the simultaneous switching noise refers to the noise caused according to large fluctuations in the power supply and the ground potential when many signals are switched at the same timing to feed a high current through a circuit.
In the case of the synchronous bus, even if simultaneous switching noise is caused, there is no problem in data transmission itself provided that the simultaneous switching noise is suppressed until the next signal synchronization. However, in the case of the asynchronous bus, if the state of a control signal such as a writing request signal is changed, the function of the control signal becomes effective, which may cause a malfunction in data transmission.
Therefore, in order to reduce simultaneous switching noise, various techniques have been proposed.
For example, in a method of arranging a buffer for generating a time difference between signals, fluctuations are caused in the time difference generated by the arranged buffer, for example, when fluctuations at the time of manufacturing, design rules, and manufacturing processes are changed. In order to accurately control the time difference between the signals, it is necessary to select an optimum buffer with respect to the time difference every time they are changed. Moreover, in this method, it is not possible to set the presence or absence of the generation of the time difference between the signals. Furthermore, in a method of lowering the current driving ability of a buffer, the switching noise of signals and simultaneous switching noise are reduced. However, in this method, electrical characteristics such as the rise time and the fall time of the signals are changed. Therefore, there may be a possibility of affecting compatibility such as disabling of components that have normally operated before the current driving ability has been changed. A buffer circuit considering an operating speed when the voltage of a power supply is lowered has been proposed, but its circuit configuration is complicated. Therefore, electrical characteristics affecting compatibility such as the driving ability of a signal output may be changed (see, for example, JP-A-8-84063).